Lead Design Engineer

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Job Description

Be part of the Cadence DDR PHY IP Front End Design team responsible for -

•             Develop firmware for DDR5 PHY using microcontrollers

•             Developing firmware in C typically involving bare-metal programming and developing low-level APIs on Microcontrollers.

•             Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them.

•             Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan.

•             Develop and Debug firmware in RTL based hardware simulations (C +Verilog simulations)

•             Develop and Debug on Silicon bring-up boards.

Required Skills:

•             Good Knowledge of DDR5 JEDEC spec, knowledge of different DIMM configurations and specifications.

•             Relevant experience in developing bare-metal firmware for High-speed SerDes or Memory interface Physical Layer blocks.

•             Good Knowledge of C programming language for embedded software development and use of relevant IDE.

•             Comfortable debugging RTL simulations involving firmware and microcontroller subsystem.

•             Good knowledge of Shell/Perl/Python/TCL scripting

•             Good experience on Verification EDA Tools like simulators and waveform viewers

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